1. Field of the Invention
The present invention relates to a data holding device, and more particularly to a data holding device having a data holding circuit for holding data in a volatile way.
2. Description of the Related Art
As a data holding circuit used for such a sequence circuit as a latch circuit, a circuit where two inverters are series-connected in a loop, for example, is known. Such a data holding circuit, however, normally can hold data only in a volatile way, so data is lost if power is shut OFF. In other words, the data before a power down cannot be restored even when power is turned back ON.
Therefore when sequence processing using such a sequence circuit is interrupted for any reason, for example, the power must be kept ON to hold the data, which wastes power. Also if sequence processing is interrupted for such a reason as an accidental power failure, the processing must be executed again from the beginning, which increases loss in processing time.
To solve such a problem, various circuits using a ferroelectric material, such as stated in U.S. Pat. No. 6,314,016, Japanese Patent Laid-Open No. 2000-124776, and U.S. Pat. No. 6,240,013 have been proposed.
U.S. Pat. No. 6,314,016 or U.S. Pat. No. 6,240,013 disclose a technology to use ferroelectric transistors, represented as an MFMIS (metal/ferroelectric/metal/insulator/semiconductor) type FET (Field Effect Transistor) as a non-volatile storage element. However, problems remain to turn a ferroelectric transistor into practical use, so a ferroelectric transistor has not yet been commercialized.
Japanese Patent Laid-Open No. 2000-124776 discloses a technology to use a ferroelectric capacitor, which is frequently seen in commercial use for a non-volatile memory device. However, in these publications, data is restored using parasitic capacity as the load capacity, along with the ferroelectric capacitor. For the parasitic capacity, where it is difficult to implement the capacity value as designed and errors in manufacturing steps are high, it is difficult to secure a detection margin to restore the data.
Even if a dedicated capacitor is installed as the load capacity, the load capacity does not store data in a non-volatile way, and dispersion occurs during manufacturing steps, so it is difficult to expect an increase of the detection margin for data restoration.
It is an object of the present invention to provide a practical device which solves the problems of such a conventional data holding circuit, and can hold data even if the power supply is shut OFF, and more particularly a data holding device which has high reliability with a large detection margin at data restoration.
A data holding device according to an embodiment of the present invention comprises a data holding circuit for holding data in a volatile way, a pair of signal lines to which signals can be applied independently from each other, and a composite capacitor comprising a pair of ferroelectric capacitors which are connected in a series, where a connection node is connected to a storage node of the data holding circuit and both ends thereof are connected to the pair of signal lines separately, wherein the polarization status corresponding to the data held in the data holding circuit is held by each one of the pair of ferroelectric capacitors by applying predetermined signals for writing to the pair of signal lines at least before the supply of power is stopped, and the data is restored in the data holding circuit based on the potential, which is generated in the connection node of the composite capacitor by applying a pair of signals for reading with different potentials to the pair of signal lines when the power supply restarts.
Since a pair of ferroelectric capacitors are used for restoring data, instead of a parasitic capacitor, it is easy to manufacture the data holding device as designed, and errors in the manufacturing steps are small. Therefore reliability in the data restoration when power returns is high.
A pair of polarization statuses corresponding to the data of the storage node of the data holding circuit are held in the pair of ferroelectric capacitors respectively. To read the data, a pair of signals for reading, having different potentials, are applied to both ends of the composite capacitor, and data is restored based on the voltage which is generated in the connection nodes of the composite capacitor depending on the pair of polarization statuses held in the pair of ferroelectric capacitors. Therefore the detection margin at data restoration can be increased compared with the case when data is held only in one ferroelectric capacitor.
In other words, a practical data holding device which can hold data even if power is shut OFF, and which has high reliability with a large detection margin at data restoration, can be implemented.
In this data holding device, it is possible that the saturation voltages of the pair of ferroelectric capacitors are substantially set to xc2xd or less of the amplitude voltage of the data in the data holding circuit respectively, the voltage within the range of the amplification voltage of the data in the data holding circuit is applied to each one of the pair of signal lines as the predetermined signals for writing, a potential substantially the same as the potential of the high level data in the data holding circuit is applied to one of the signal lines, and a potential substantially the same as the potential of the low level data in the data holding circuit is applied to the other signal line as a pair of signals for reading. Or, in this data holding device, it is also possible that the saturation voltage of the pair of ferroelectric capacitors is substantially the same or less than the amplitude voltage of the data in the data holding circuit respectively, a pulse signal, where the top potential is a potential substantially the same as the potential of the high level data in the data holding circuit and the bottom potential substantially the same as the potential of the low level data in the data holding circuit, is applied to each one of the pair of signal lines as the predetermined signals for writing, and a potential substantially the same as the potential of the high level data in the data holding circuit is applied to one of the signal lines, and a potential substantially the same as the potential of the low level data in the data holding circuit is applied to the other signal line as a pair of signals for reading.
Therefore in this data storage device, a pair of voltages corresponding to the data held in the data holding circuit, which is higher than the saturation voltage of the ferroelectric capacitor, can be applied to the pair of ferroelectric capacitors respectively by applying the signals for writing to the pair of signal lines. So a pair of remanent polarizations corresponding to the data can be generated at each one of the pair of ferroelectric capacitors without fail.
By applying signals for reading to the pair of signal lines, a voltage substantially the same as the amplitude voltage of the data in the data holding circuit can be applied to the composite capacitor. Therefore a voltage with a large margin corresponding to the data is generated at the connection point of the composite capacitor.
In the data holding device, it is possible that predetermined signals for writing are steadily applied to the pair of signal lines while power is supplied, or predetermined signals for writing are applied during only a predetermined period before the power supply is stopped. In the former case, it is not necessary for the signals lines to perform a special operation when power is shut OFF, so circuits can be simplified. In the latter case, polarization inversion of the ferroelectric capacitor rarely occurs during normal operation, so deterioration of the ferroelectric capacitors can be decreased even if quality of the ferroelectric capacitor is not good.
In this data holding device, it is possible that the data holding circuit includes a pair of inverter circuits which can be series-connected in a loop, and can connect the connection node of the composite capacitor to the input node of one inverter circuit of the pair of inverter circuits.
Therefore in the volatile data holding circuit which is generally used, the output of the inverter circuit to which the connection node of the composite capacitor is connected, can be returned to the status before power was shut OFF without fail.
Also in this data holding device, it is possible that the output node of the inverter circuit installed on a feedback path, out of the pair of inverter circuits, is connected to the input node of the inverter circuit installed on a main signal path via a gate for enabling/disabling feedback signals, the connection node of the composite capacitor is connected to the input node of the inverter circuit installed on the main signal path, and the pair of signals for reading are applied to the pair of signal lines while maintaining the gate for enabling/disabling feedback signals as disabled status when the power supply restarts, then the gate for enabling/disabling feedback signals is set to enable status.
When the power supply is restarted, the output of the inverter circuit installed on the feedback path is unstable, so such an output, being input to the input node of the inverter circuit installed on the main signal path, is blocked. Therefore only the potential, which was generated in the connection node of the composite capacitor of a pair of signals for reading, is applied to the input node of the inverter circuit installed on the main signal path at initialization when the power supply is restarted. In this way, the contention of signals, when the power supply is restarted, is prevented, so as to further improve the reliability of data restoration.
Also the contention of signals when the power supply is restarted is prevented using the gate for enabling/disabling feedback signals generally used for the latch circuit, so the contention of signals can be prevented without separately controlling the power supplies of the pair of inverter circuits when the power supply is restarted. Therefore the circuit configuration can be simplified.
In addition to the above embodiments, the present invention can be an electronic circuit comprising a gate for enabling/disabling signals, controlled based on the data held in the data holding device above described.
Therefore if the gate for enabling/disabling signals for connecting logical blocks in large scale logical circuits, such as DPGA (Dynamic Programmed Gate Array), is controlled based on the data held in the data holding device, then the enable/disable information is held without fail even when the power supply is shut OFF, so this invention is especially useful for decreasing power consumption.